DSP implementation of a Range Azimuth CFAR processor

Author

Magaz, B. ; Bencheikh, M.L.

Author_Institution

R&D Center, Algiers

fYear

2008

fDate

21-23 May 2008

Firstpage

1

Lastpage

4

Abstract

In this paper, we present DSP architecture for target detection based on range azimuth cell averaging constant false alarm rate (ARCA-CFAR) processor with non coherent integration. The proposed architecture has been designed to deal with parallel processing and to be configured for the RACA-CFAR algorithm implementation. The design has been implemented on a Texas Instruments TMS320C6711 digital signal processor board with a good performance improvement. The proposed system scheme and the real time implementation results are presented and discussed in this paper.

Keywords

digital signal processing chips; radar signal processing; radar target recognition; DSP architecture; DSP implementation; digital signal processor board; parallel processing; range azimuth CFAR processor; range azimuth cell averaging constant false alarm rate processor; target detection; Algorithm design and analysis; Azimuth; Digital signal processing; Digital signal processors; Instruments; Object detection; Parallel processing; Real time systems; Signal design; Signal processing algorithms; CFAR; DSP TMS320C6711; Implementation; Range Azimuth;

fLanguage

English

Publisher

ieee

Conference_Titel

Radar Symposium, 2008 International

Conference_Location

Wroclaw

Print_ISBN

978-83-7207-757-8

Type

conf

DOI

10.1109/IRS.2008.4585780

Filename

4585780