• DocumentCode
    2371983
  • Title

    Bitwise aggregate networks

  • Author

    Hoare, R. ; Dietz, H. ; Mattox, I. ; Kim, S.

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • fYear
    1996
  • fDate
    23-26 Oct 1996
  • Firstpage
    306
  • Lastpage
    313
  • Abstract
    Typical communication networks for parallel processing are based on sending data from one processor to one, or all, of the other processors. Using such a network, many simple operations that require information from every processor requires many point-to-point or broadcast communications. These aggregate operations can be as simple as a barrier synchronization or as complex as an arithmetic reduction. In this paper we discuss a class of networks that directly implement a wide range of aggregate operations. These networks are capable of performing aggregate operations in a single communication operation using only simple bitwise combining logic in a trivially scalable tree configuration
  • Keywords
    multiprocessor interconnection networks; parallel architectures; aggregate networks; barrier synchronization; bitwise combining logic; communication networks; parallel processing; scalable tree configuration; Aggregates; Broadcasting; Clocks; Computer networks; Concurrent computing; Data engineering; Delay; Hardware; Logic; Signal processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing, 1996., Eighth IEEE Symposium on
  • Conference_Location
    New Orleans, LA
  • Print_ISBN
    0-8186-7683-3
  • Type

    conf

  • DOI
    10.1109/SPDP.1996.570348
  • Filename
    570348