DocumentCode
2372053
Title
Locality aware redundancy allocation in nanoelectronic systems
Author
Rao, Wenjing ; Orailoglu, Alex ; Marzullo, Keith
Author_Institution
ECE Dept., Univ. of Illinois at Chicago, Chicago, IL
fYear
2008
fDate
12-13 June 2008
Firstpage
24
Lastpage
31
Abstract
A high level of redundancy is required to deal with the challenge of high defect and fault rates in nano environments. The reconfigurability of nano devices and the regular structure of nano fabrics make reconfiguration based repair an essential approach for both defect and fault tolerance. Ideally, repair based approaches have the best hardware efficiency when full sharing of redundancy is achievable. However, nanoelectronic systems are subject to strict constraints on localized interconnections, which limit the sharing of redundant resources to within a small neighborhood. To more fully understand this challenge, we provide a model for the issue of redundant resource sharing under locality constraint. Our model captures the redundancy sharing essence of a system, and is applicable to any specific topology or layout of a nanoelectronic system. Based on this model, defect tolerance can be well defined, and can be addressed by existing algorithms. In addition, we provide discussion and algorithms for online fault tolerance for various system models. Overall, this paper provides a new framework and novel solutions to a the problem of reliability in nanoelectronic environments, where locality constraint for redundancy sharing plays an important role in developing defect / fault tolerance schemes.
Keywords
fault tolerance; integrated circuit interconnections; integrated circuit reliability; nanoelectronics; defect-fault tolerance schemes; hardware efficiency; locality aware redundancy allocation; nanoelectronic environments, reliability; nanoelectronic systems; repair based approaches; CMOS technology; Delay; Fabrication; Fault tolerance; Hardware; Integrated circuit interconnections; Nanoscale devices; Power system interconnection; Redundancy; Self-assembly;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanoscale Architectures, 2008. NANOARCH 2008. IEEE International Symposium on
Conference_Location
Anaheim, CA
Print_ISBN
978-1-4244-2552-5
Electronic_ISBN
978-1-4244-2553-2
Type
conf
DOI
10.1109/NANOARCH.2008.4585788
Filename
4585788
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