• DocumentCode
    2372138
  • Title

    Reconfigurable BDD based quantum circuits

  • Author

    Eachempati, Soumya ; Saripalli, Vinay ; Vijaykrishnan, N. ; Datta, Suman

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
  • fYear
    2008
  • fDate
    12-13 June 2008
  • Firstpage
    61
  • Lastpage
    67
  • Abstract
    We propose a novel binary decision diagram (BDD) based reconfigurable logic architecture based on split-gate quantum nanodots using III-V compound semiconductor-based quantum wells. While BDD based quantum devices architectures have already been demonstrated to be attractive for achieving ultra-low power operation, our design provides the ability to reconfigure the functionality of the logic architecture. This work proposes device and architectural innovations to support such reconfiguration. At the device level, a unique programmability feature is incorporated in our proposed nanodot devices which can operate in 3 distinct operation modes: a) active b) open and c) short mode based on the split gate bias voltages and enable functional reconfiguration. At the architectural level, we address programmability and design fabric issues involved with mapping BDDpsilas into a reconfigurable architecture. By mapping a set of logic circuits, we demonstrate that our underlying device and architectural structure is flexible to support different functions.
  • Keywords
    III-V semiconductors; binary decision diagrams; logic circuits; quantum dots; quantum well devices; III-V compound semiconductor-based quantum wells; binary decision diagram; logic architecture; reconfigurable BDD based quantum circuits; reconfigurable logic architecture; split gate bias voltages; split-gate quantum nanodots; ultralow power operation; Binary decision diagrams; Boolean functions; Circuits; Data structures; III-V semiconductor materials; Logic design; Logic devices; Reconfigurable logic; Split gate flash memory cells; Technological innovation; Low power; Quantum nanodevice; Reconfigurability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanoscale Architectures, 2008. NANOARCH 2008. IEEE International Symposium on
  • Conference_Location
    Anaheim, CA
  • Print_ISBN
    978-1-4244-2552-5
  • Electronic_ISBN
    978-1-4244-2553-2
  • Type

    conf

  • DOI
    10.1109/NANOARCH.2008.4585793
  • Filename
    4585793