• DocumentCode
    2372182
  • Title

    A new charge-trap-engineered memory device with Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) structure for LTPS-TFT-based applications

  • Author

    Liao, Ta-Chuan ; Wu, Chun-Yu ; Chen, Sheng-Kai ; Yu, Ming H. ; Kang, Tsung-Kuei ; Cheng, Huang-Chung

  • Author_Institution
    Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    2010
  • fDate
    6-8 Dec. 2010
  • Abstract
    For the first time, a new Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) LTPS-TFT-based charge-trapping memory integrated on a gate-all-around field-enhanced-nanowire architecture was demonstrated. The vacuum, simply formed by an in-situ encapsulation, substituted for the traditional tunneling oxide. Due to the lowest-k and empty properties of vacuum, SONVAS features electric field enhancement in tunneling layer and immunity against the creation of interface traps and the charge trapping in the damaged tunneling oxide during P/E cycling, resulting in the much-improved P/E efficiency and reliability, respectively. Therefore, such vacuum-introduced SONVAS memory device with process simplicity is very suitable for the future system-on-panel (SOP) and 3D-stacking flash applications.
  • Keywords
    encapsulation; flash memories; interface states; nanoelectronics; nanowires; silicon compounds; thin film transistors; 3D-stacking flash memory; P/E cycling; SONVAS LTPS-TFT; SiON-Si; charge-trap-engineered memory device; electric field enhancement; gate-all-around field-enhanced-nanowire architecture; in-situ encapsulation; interface traps; silicon-oxide-nitride-vacuum-silicon structure; system-on-panel; tunneling oxide;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0163-1918
  • Print_ISBN
    978-1-4424-7418-5
  • Electronic_ISBN
    0163-1918
  • Type

    conf

  • DOI
    10.1109/IEDM.2010.5703489
  • Filename
    5703489