2372509

5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

Vangal, S. ; Borkar, N. ; Seligman, E. ; Govindarajulu, V. ; Erraguntla, V. ; Wilson, H. ; Pangal, A. ; Veeramachaneni, V. ; Anders, M. ; Tschanz, J. ; Ye, Y. ; Somasekhar, D. ; Bloechel, B. ; Dermer, G. ; Krishnamurthy, R. ; Narendra, S. ; Stan, M. ; Tho

Intel Corporation

2

2002

7-7 Feb. 2002

334

535

Adders; Circuit testing; Clocks; Delay; Flip-flops; Prototypes; Radio frequency; Registers; Signal design; Signal generators;

English

ieee

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

San Francisco, CA, USA

0-7803-7335-9

conf

10.1109/ISSCC.2002.992282

992282