DocumentCode

2372553

Title

The high-bandwidth 256kB 2nd-level cache on an itanium microprocessor

Author

Riedlinger, R. ; Grutkowski, T.

Author_Institution

Hewlett Packard

Volume

2

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

340

Lastpage

537

Keywords

Centralized control; Circuits; Clocks; Control systems; Error correction codes; Microprocessors; Protection; Read-write memory; Software performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992285

Filename

992285