DocumentCode
2373014
Title
0.5 μm line width molybdenum metallization for the first level interconnection
Author
Hosoya, Tetsuo ; Kanamori, Shuichi ; Namatsu, Hideo ; Takahashi, Yasuo
Author_Institution
NTT LSI Lab., Kanagawa, Japan
fYear
1991
fDate
11-12 Jun 1991
Firstpage
289
Lastpage
291
Abstract
Proposes a multilevel interconnection process using molybdenum(Mo) with 0.5 μm line width for the first level and aluminum(Al) for the second level interconnection. To apply 0.5 μm Mo features to a multilevel interconnection system, it is studied to provide better adhesion of interlevel silicon dioxide(SiO2) to Mo, to reduce the resistivities of Mo films, and to etch fine Mo patterns. The Mo metallization process developed is successfully applied to the first level interconnection with a design pitch (line and space) of 1.1 μm. Reliability tests reveal the 0.5 μm Mo metallization provides high migration immunity as expected
Keywords
VLSI; electromigration; metallisation; molybdenum; 0.5 micron; Mo metallization process; Mo-SiO2; VLSI; adhesion; design pitch; electromigration resistance; first level interconnection; migration immunity; multilevel interconnection; multilevel interconnection process; reliability issues; resistivities; Conductivity; Delamination; Electromigration; Laboratories; Large scale integration; Lithography; Metallization; Sputter etching; Sputtering; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Multilevel Interconnection Conference, 1991, Proceedings., Eighth International IEEE
Conference_Location
Santa Clara, CA
Print_ISBN
0-87942-673-X
Type
conf
DOI
10.1109/VMIC.1991.153002
Filename
153002
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