• DocumentCode
    2373194
  • Title

    Design and implementation of efficient hardware solution based sub-window architecture of Haar classifiers for real-time detection of face biometrics

  • Author

    Luo, Ren C. ; Liu, Hsin-Hung

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2010
  • fDate
    4-7 Aug. 2010
  • Firstpage
    1563
  • Lastpage
    1568
  • Abstract
    In this paper we propose a hardware solution by the use of FPGA based circuit for real time face detection. We have built a sub-window architecture for the extraction of Haar-like features, which are the basic elements of weak classifiers according to AdaBoost learning algorithm. The main contribution is that the proposed architecture removes traditional frame buffer, and only reserve the line buffer and sub-window register array. When the video data is in the progress of delivery, every pixel will be sent to the line buffer one by one and then be moved into sub-window for the circulation of weak classifiers calculation directly. Because integral image can be calculated by sub-window register array immediately, it provides the best detection performance without delay, and executes the minimal step of sub-window movement for best face detection accuracy. We have implemented hardware circuit and analyze it by Xilinx System Generator. The outcome shows that our design provides face detection speed up to 471.6 fps in the resolution of 640 × 480.
  • Keywords
    Haar transforms; buffer storage; face recognition; feature extraction; field programmable gate arrays; image classification; learning (artificial intelligence); object detection; AdaBoost learning algorithm; FPGA based circuit; Haar classifiers; Haar-like feature extraction; Xilinx System Generator; face biometrics; frame buffer; hardware circuit; hardware solution; integral image; line buffer; real-time face detection; subwindow architecture; subwindow register array; video data; Arrays; Classification algorithms; Face detection; Feature extraction; Hardware; Pixel; Registers; AdaBoost; Face detection; Field Programmable Gate Array (FPGA); Haar-like features; Xilinx System Generator;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Mechatronics and Automation (ICMA), 2010 International Conference on
  • Conference_Location
    Xi´an
  • ISSN
    2152-7431
  • Print_ISBN
    978-1-4244-5140-1
  • Electronic_ISBN
    2152-7431
  • Type

    conf

  • DOI
    10.1109/ICMA.2010.5589229
  • Filename
    5589229