Title :
Binning for IC quality: experimental studies on the SEMATECH data
Author :
Singh, D. ; Nigh, Phil
Author_Institution :
Dept. of Electr. Eng., Auburn Univ., AL
Abstract :
In semiconductor manufacturing, the observed clustering of defects on a wafer has often led to the practice of discarding die from wafers, or parts of the wafer, that display a high incidence of failures. In recent work we have formalized and refined this process with the goal of minimizing test escapes during production testing. In the new approach, in evaluating the quality of test results for a particular die, test results for the die´s neighbors are also considered. Among other results, it has been shown that by exploiting defect clustering information it is possible to bin dice following testing so as to separate out a high quality bin with defect levels up to an order of magnitude better than the average for the lot. In this paper we present the first experimental results on the effectiveness of die screening for a modern submicron CMOS process. The data comes from the SEMATECH test methods experiment conducted at IBM on 18,466 from a production ASIC in a 0.5 μm process
Keywords :
CMOS integrated circuits; application specific integrated circuits; integrated circuit manufacture; integrated circuit testing; production testing; quality control; 0.5 micron; IC quality; SEMATECH data; SEMATECH test methods; defect clustering information; die screening; die testing; high quality bin; production ASIC; production testing; semiconductor manufacturing; submicron CMOS process; Application specific integrated circuits; CMOS process; Circuit faults; Circuit testing; Cost function; Displays; Microelectronics; Production; Semiconductor device manufacture; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8832-7
DOI :
10.1109/DFTVS.1998.732145