Spur reduction techniques in direct digital synthesizers

Spur reduction techniques used in direct digital synthesizers (DDSs) or numerically controlled oscillators (NCOs) are reviewed. First, the classification and operation of conventional DDSs are reviewed. The pulse output DDS, the sine output DDS, the fractional divider, and the phase interpolation DDS are considered. It is shown that DDSs produce spurs as well as the desired output frequency due to the aliasing of harmonic imperfections in the generated waveform. Next, spur reduction techniques which reduce spurs by destroying the coherence of the aliasing process are discussed. Architectures described are the spurless fractional divider, the Wheatley jitter injection DDS, the randomized DAC (digital-to-analog) DDS, and the nonuniform clock DDS. The spur reduction and phase jitter properties of each architecture are also discussed