DocumentCode
2373712
Title
On-chip test embedding for multi-weighted random LFSRs
Author
Kagaris, D. ; Tragoudas, S. ; Majumdar, A.
Author_Institution
Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
fYear
1998
fDate
2-4 Nov 1998
Firstpage
135
Lastpage
143
Abstract
We present for the first time a systematic approach for partitioning deterministic test set into subsets so that multiple weight-sets, one weight-set per subset, are generated for efficient Weighted Random LFSR Test Pattern Generation. The basic partitioning criterion is the maximum Hamming distance between any two test patterns in the same set. The number of test patterns within each subset is also taken into consideration. The proposed tools make use of optimal partitioning algorithms. Experimental results clearly indicate the effectiveness of the proposed scheme
Keywords
automatic test pattern generation; circuit feedback; integrated circuit testing; shift registers; Hamming distance; automatic test pattern generation; deterministic test set; linear feedback shift register; multi-weighted random LFSR; on-chip test embedding; partitioning algorithm; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Conference_Location
Austin, TX
ISSN
1550-5774
Print_ISBN
0-8186-8832-7
Type
conf
DOI
10.1109/DFTVS.1998.732160
Filename
732160
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