Title :
The composite DDS A new direct digital synthesizer architecture
Author :
Kushner, Lawrence J.
Author_Institution :
Lincoln Lab., MIT, Lexington, MA, USA
Abstract :
A novel low-power, high-speed, direct digital synthesizer (DDS) architecture is presented, called the composite DDS (CDDS). A low-speed, high-resolution DDS is combined with a high-speed, low-resolution DDS is combined with a high-speed, low-resolution phase accumulator and phase shifter via the serrodyne modulation technique. The low-speed circuitry provides a fine tuning while the high-speed circuitry provides coarse tuning. By minimizing the amount of circuitry required to clock at high speeds, DC power is conserved. Results from numeric simulations and a low-frequency proof-of-consents breadboard are presented. Progress on an 800-MHz CDDS development effort is described, and proposed enhancements to the CDDS architecture which promise improved performance are discussed
Keywords :
CMOS digital integrated circuits; UHF generation; UHF integrated circuits; circuit tuning; direct digital synthesis; frequency synthesizers; 800 MHz; CDDS architecture; CMOS low-speed DDS; DC power; GaAs HBT modulator; composite DDS; direct digital synthesizer architecture; low-frequency proof-of-consents breadboard; numeric simulations; phase accumulator; phase shifter; serrodyne modulation technique; Bandwidth; Circuit optimization; Clocks; Energy consumption; Frequency conversion; Laboratories; Phase modulation; Phase shifters; Power generation; Synthesizers;
Conference_Titel :
Frequency Control Symposium, 1993. 47th., Proceedings of the 1993 IEEE International
Conference_Location :
Salt Lake City, UT
Print_ISBN :
0-7803-0905-7
DOI :
10.1109/FREQ.1993.367404
