Title :
A new method for testing EEPLAs
Author :
Munshi, A. ; Meyer, F.J. ; Lombardi, F.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Abstract :
We present a new method for testing electrically erasable programmable logic arrays (EEPLA) under multiple faults. These include line stuck-at faults, bridging faults, and crosspoint faults. Our proposed method achieves 100% fault coverage of multiple faults by reprogramming the EEPLA many times. The complexity of testing EEPLAs is largely dependent on the number of programming phases, because programming time is much larger than test application time. The proposed method achieves a substantial reduction in programming phases compared with prior methods; and, thereby, in testing time, even though it involves more test vectors. The programming is based on a parallel sequence in which a larger number of crosspoints are tested per phase-a toroidal sequence with which full coverage is still guaranteed. We analyze the method to obtain the testing time as a function of the numbers of input variables, product lines, and output functions
Keywords :
automatic testing; fault diagnosis; logic testing; programmable logic arrays; EEPLAs; bridging faults; crosspoint faults; crosspoints; electrically erasable programmable logic arrays; input variables; line stuck-at faults; multiple faults; output functions; parallel sequence; product lines; programming phases; programming time; reprogramming; test application time; test vectors; testing time; toroidal sequence; Circuit faults; Circuit testing; Computer science; Hardware; Input variables; Logic programming; Logic testing; Manufacturing; Parallel programming; Programmable logic arrays;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8832-7
DOI :
10.1109/DFTVS.1998.732161