Real-Time Stereo Vision Processing System in a FPGA

This paper describes a reconfigurable digital architecture to compute dense disparity maps at video-rate for stereo vision. The processor architecture is described in synthetizable VHDL and, by means of the reconfigurability, the hardware requirements are optimized for different image resolutions and matching scenarios. The configurable description of a stereo processor provides the entity to design stereo matching systems, implementing by incremental design multi-baseline or multi-scale stereo vision algorithms. We show the results of the synthesis and its implementation cost in logic elements and time delays. The synthesis results have been implemented in a practical prototype