Self-reconfiguration scheme of 3D-mesh arrays

Author

Horiguchi, Susumu ; Numata, Issei

Author_Institution

Graduate Sch. of Inf. Sci., Adv. Inst. of Sci. & Technol., Ishikawa, Japan

fYear

1998

fDate

2-4 Nov 1998

Firstpage

276

Lastpage

281

Abstract

Addresses a self-reconfiguration scheme of 3D-mesh arrays. The reconfiguration performance of 3D-mesh is obtained for 3D 1½. We demonstrated that the proposed HS-scheme achieves high system yield without global information. Although 2D-mesh with 8000 PEs requires much more than 90 x 90 PEs, 3D-mesh array becomes a compact size of arrays. It is seen that the HS-scheme dose not achieve high array yield for a large size ED-mesh since the number of tracks is limited. However, the HS-scheme can be widely applied to 3D-mesh consisting of more PEs, more spare PEs, and more tracks, although other schemes are only for 3D 1½

Keywords

VLSI; fault tolerant computing; integrated circuit yield; multiprocessing systems; parallel architectures; 3D-mesh arrays; HS-scheme; VLSI; array yield; large scale parallel computers; large size ED-mesh; multiprocessor systems; self-reconfiguration scheme; system yield; Circuit faults; Concurrent computing; Information science; Integrated circuit interconnections; Multiprocessing systems; Silicon; Supercomputers; Switches; Switching circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on

Conference_Location

Austin, TX

ISSN

1550-5774

Print_ISBN

0-8186-8832-7

Type

conf

DOI

10.1109/DFTVS.1998.732176

Filename

732176