A system for evaluating on-line testability at the RT-level

This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an exploration of different testable architectures before committing to the final design. Circuits are modeled as finite state machines, and a set of transformations can be defined inside the system to account for different on-line test strategies. Preliminary experiments show that the information made available by the evaluation system can be used to drive the testable design process towards a better trade-off point