Designing for yield: a defect-tolerant approach to high-level synthesis

Defect-tolerant techniques can be effectively applied to regular structures which allow a very simple reconfiguration technique. A typical example is represented by memories, where algorithms for row and column elimination grant very good results with a limited area overhead (namely, a limited number of spare rows and columns). The reconfiguration technologies developed for memories could be applied to other devices only if the two conditions of regularity and simplicity can be transferred to their architectures. In the present paper we propose a methodology aiming at designing an intrinsically regular data path thus achieving defect-tolerance with a limited area increase, both in terms of spare functional units and memories and in terms of augmented interconnection network