A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling

Author

Truong, Dean ; Cheng, Wayne ; Mohsenin, Tinoosh ; Yu, Zhiyi ; Jacobson, Toney ; Landge, Gouri ; Meeuwsen, Michael ; Watnik, Christine ; Mejia, Paul ; Tran, Anh ; Webb, Jeremy ; Work, Eric ; Xiao, Zhibin ; Baas, Bevan

Author_Institution

Univ. of California, Davis, CA

fYear

2008

fDate

18-20 June 2008

Firstpage

22

Lastpage

23

Abstract

A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and three 16 KB shared memories, all clocked by independent oscillators and connected by configurable long-distance-capable links.

Keywords

digital signal processing chips; nanoelectronics; DSP; algorithm-specific processors; configurable long-distance-capable links; dynamic clock frequency scaling; dynamic supply voltage; independent oscillators; multimedia workloads; programmable processors; shared memories; size 65 nm; Circuits; Clocks; Digital signal processing chips; Dynamic voltage scaling; Frequency; Local oscillators; Power grids; Tiles; Viterbi algorithm; Voltage control; DSP; DVFS; GALS; many-core;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2008 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1804-6

Electronic_ISBN

978-1-4244-1805-3

Type

conf

DOI

10.1109/VLSIC.2008.4585936

Filename

4585936