A 26mW 6.4GFLOPS multi-core stream processor for mobile multimedia applications

Author

Tsao, You-Ming ; Sun, Chih-Hao ; Lin, Yu-Cheng ; Lok, Ka-Hang ; Hsu, Chia-Jung ; Chien, Shao-Yi ; Chen, Liang-Gee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

fYear

2008

fDate

18-20 June 2008

Firstpage

24

Lastpage

25

Abstract

A 26 mW 6.4 GFLOPS multi-core stream processor for mobile applications is implemented in 90 nm CMOS technology. A unified stream processing architecture with power-aware frequency scaling and adaptive task scheduling techniques are proposed to reduce the power consumption and increase the performance to achieve the performance of 200 Mvertices/s and 400 Mpixels/s in 3D graphic applications.

Keywords

CMOS integrated circuits; coprocessors; low-power electronics; mobile computing; multimedia computing; scheduling; 3D graphic applications; CMOS technology; GFLOPS multicore stream processor; adaptive task scheduling techniques; mobile multimedia applications; power 26 mW; power consumption reduction; power-aware frequency scaling; size 90 nm; unified stream processing architecture; Adaptive scheduling; Control systems; Engines; Frequency; Graphics; Kernel; Processor scheduling; Reduced instruction set computing; Streaming media; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2008 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1804-6

Electronic_ISBN

978-1-4244-1805-3

Type

conf

DOI

10.1109/VLSIC.2008.4585937

Filename

4585937