• DocumentCode
    2374975
  • Title

    A 40Gb/s low-power analog equalizer in 0.13μm CMOS technology

  • Author

    Lu, Jian-Hao ; Chen, Ke-Hou ; Liu, Shen-Iuan

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
  • fYear
    2008
  • fDate
    18-20 June 2008
  • Firstpage
    54
  • Lastpage
    55
  • Abstract
    A 40 Gb/s low-power analog equalizer has been realized in 0.13 mum CMOS technology. To achieve a peaking gain of 10 dB at 20 GHz and low power dissipation, an inductive feedback stage is proposed. This inductive feedback stage consumes 3.6 mW from a 1.2 V supply and the whole equalizer consumes 14.4 mW. The chip occupies 0.57 times 0.44 mm2. For a 40 Gb/s PRBS of 27-1, the measured BER is less than 10-12 and the measured maximum peak-to-peak jitter is 12.6 ps.
  • Keywords
    CMOS analogue integrated circuits; equalisers; error statistics; low-power electronics; random number generation; BER; CMOS technology; PRBS; analog equalizer; bit error rate; bit rate 40 Gbit/s; inductive feedback stage; low power dissipation; power 3.6 mW; pseudorandom binary sequence; size 0.13 mum; voltage 1.2 V; Bandwidth; Bit error rate; CMOS technology; Equalizers; Frequency; Inductance; Jitter; Output feedback; Power dissipation; Semiconductor device measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2008 IEEE Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-1804-6
  • Electronic_ISBN
    978-1-4244-1805-3
  • Type

    conf

  • DOI
    10.1109/VLSIC.2008.4585949
  • Filename
    4585949
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2374975