A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology

The design and experimental results of a low-power, low-area 5-tap DFE implemented in 45-nm SOI CMOS technology are reported. The DFE employs a low-power current-integrating summer with sampling front-end, which eliminates systematic frequency-dependent loss inherent in conventional integrating serial receivers. Further power and area savings are achieved through the use of a direct-feedback architecture and CMOS-style rail-to-rail clocking. The 5-tap DFE core occupies 73 times 50 mum² and consumes 11 mW from a 1V supply when equalizing 12-Gb/s data passed over a 30rdquo channel with 15 dB of loss at 6 GHz.