Next generation Intel® micro-architecture (Nehalem) clocking architecture

Author

Kurd, Nasser ; Douglas, Jonathan ; Mosalikanti, Praveen ; Kumar, Rajesh

Author_Institution

Intel Corp., Hillsboro, OR

fYear

2008

fDate

18-20 June 2008

Firstpage

62

Lastpage

63

Abstract

This paper describes the next generation Intel^reg micro-architecture (Nehalem) 45 nm IA processorpsilas core and I/O clocking architecture. Among the highlights are: configurable clocking, fastlock low-skew PLLs, high reference clock frequencies, analog supply tracking system, adaptive frequency clocking, low jitter Intel^reg QuickPath interconnect and Intel^reg QuickPath memory controller clock generation, and jitter-attenuating DLLs.

Keywords

clocks; integrated memory circuits; microprocessor chips; phase locked loops; I/O clocking architecture; Intel QuickPath interconnect; Intel QuickPath memory controller clock generation; Intel micro-architecture; Nehalem; PLL; adaptive frequency clocking; analog supply tracking system; jitter-attenuating DLL; Adaptive control; Clocks; Communication system control; Control systems; Frequency; Integrated circuit interconnections; Jitter; Phase locked loops; Programmable control; Voltage; DLL; IA; Intel® QuickPath; PLL; interconnect; memory controller;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2008 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1804-6

Electronic_ISBN

978-1-4244-1805-3

Type

conf

DOI

10.1109/VLSIC.2008.4585952

Filename

4585952