• DocumentCode
    2375094
  • Title

    A 1.2V 30mW 8b 800MS/s time-interleaved ADC in 65nm CMOS

  • Author

    Tu, Wei-Hsuan ; Kang, Tzung-Hung

  • Author_Institution
    MediaTek Inc., Hsinchu
  • fYear
    2008
  • fDate
    18-20 June 2008
  • Firstpage
    72
  • Lastpage
    73
  • Abstract
    An 8-bit 800 MS/s time-interleaved pipeline ADC with SNDR of 47.8 dB and 44.2 dB for 1 MHz and 400 MHz inputs is presented. The techniques of sub-ADC preamp sharing and reference voltage buffer current-reusing are proposed to minimize power consumption. The ADC implemented in 65 nm digital CMOS process with an active area of 0.12 mm2 consumes 30 mW from a 1.2 V supply and achieves a FOM of 0.28 pJ/conversion-step.
  • Keywords
    CMOS digital integrated circuits; analogue-digital conversion; buffer circuits; preamplifiers; digital CMOS process; power 30 mW; power consumption minimization; reference voltage buffer current-reusing; sub-ADC preamp sharing; time-interleaved ADC; voltage 1.2 V; CMOS process; Delay; Energy consumption; Latches; Low voltage; MOS devices; Pipelines; Sampling methods; Switches; Switching circuits; Time-interleaved pipeline ADC; low power;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2008 IEEE Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-1804-6
  • Electronic_ISBN
    978-1-4244-1805-3
  • Type

    conf

  • DOI
    10.1109/VLSIC.2008.4585956
  • Filename
    4585956
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2375094