DocumentCode
2375113
Title
A 1.2V 250mW 14b 100MS/s digitally calibrated pipeline ADC in 90nm CMOS
Author
De Vel, Hans Van ; Buter, Berry ; Van der Ploeg, Hendrik ; Vertregt, Maarten ; Geelen, Govert ; Paulus, Edward
Author_Institution
NXP Semicond., Eindhoven
fYear
2008
fDate
18-20 June 2008
Firstpage
74
Lastpage
75
Abstract
A 14 b pipeline ADC is realized in 90 nm CMOS at a 1.2 V supply. Enabling techniques are range-scaling in the first pipeline stage with charge-reset and digital background calibration of non-linearity. The ADC achieves 73 dB SNR and 91 dB SFDR at 100 MS/s sampling rate and 250 mW power consumption. The 73 dB SNDR performance is maintained within 3 dB up to a Nyquist input frequency and the FOM is 0.7 pJ/conv.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; CMOS; Nyquist input frequency; charge-reset; digital background calibration; digitally calibrated pipeline ADC; noise figure 73 dB; power 250 mW; size 90 nm; voltage 1.2 V; Calibration; Capacitance; Capacitors; Feedback; Interference; Low voltage; Nonlinear distortion; Pipelines; Sampling methods; Switches; A/D conversion; deep-submicron CMOS and low supply voltage; digital calibration; pipeline ADC;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-1804-6
Electronic_ISBN
978-1-4244-1805-3
Type
conf
DOI
10.1109/VLSIC.2008.4585957
Filename
4585957
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