Title :
A 256mW full-HD H.264 high-profile CODEC featuring dual macroblock-pipeline architecture in 65nm CMOS
Author :
Iwata, Kenichi ; Mochizuki, Seiji ; Shibayama, Tetsuya ; Izuhara, Fumitaka ; Ueda, Hiroshi ; Hosogi, Koji ; Nakata, Hiroaki ; Ehama, Masakazu ; Kengaku, Toru ; Nakazawa, Takuichiro ; Watanabe, Hiromi
Author_Institution :
Renesas Technol. Corp., Tokyo
Abstract :
A video-size-scalable H.264 high-profile CODEC including 19 specific CPUs for extensibility to multiple standards has been fabricated in 65 nm CMOS. With two parallel pipelines for macroblock processing, the CODEC consumed 256 mW in real-time encoding of full-HD (1080i) video at an operating frequency of 162 MHz. It represents a 38% reduction in power consumption per pixel compared with state-of-the-art designs.
Keywords :
CMOS integrated circuits; video codecs; video coding; CMOS; dual macroblock-pipeline architecture; full-HD H.264 high-profile CODEC; macroblock processing; power 256 mW; real-time encoding; Clocks; Delay; Energy consumption; Frequency; High definition video; Pipelines; SDRAM; Streaming media; Video codecs; Video coding;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585968
