Title :
A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution
Author :
Lee, Minjae ; Heidari, Mohammad E. ; Abidi, Asad A.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA
Abstract :
A digital PLL uses a high resolution coarse-fine time-to-digital converter (TDC) for wide loop bandwidth. The loop bandwidth is set to 400 kHz with a 26 MHz reference for GSM. The in-band phase noise contribution from the TDC is -116 dBc/Hz, the phase noise is -117 dBc/Hz at high-band 400 kHz offset, and the RMS phase error is 0.3deg.
Keywords :
cellular radio; digital phase locked loops; GSM; in-band phase noise contribution; low noise phase-locked loop; subpicosecond resolution; time-to-digital converter; wideband digital phase-locked loop; Bandwidth; Clocks; Counting circuits; Delay effects; Flip-flops; Frequency conversion; Phase locked loops; Phase noise; Quantization; Wideband; digital phase-locked loop (PLL); residue amplification; wide bandwidth and time-to-digital converter (TDC);
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585972
