Design and implementation of tree decoder for SDR applications

The key objective of this project is to design a decoder which can be used for hardware purposes. Hardware, here accompanies with software which is more we can discuss as a Software Defined Radio application. The decoder implemented here offers to new radio equipment (SDR), the flexibility of a programmable system. Nowadays, the behavior of a communication system can be modified by simply changing its software. Large tree decoder can be constructed by reusing smaller similar sub-modules. Thus the structure is symmetric. The symmetric and regular structure of tree decoder makes the system easy to design. The structure obeys regularity and modularity concepts of VLSI circuit, thus is easy to fabricate using cell library elements. Design a Tree Decoder proposed architecture for SDR application on FPGA. The Structures made here are hardware synthesizable on FPGA board and are done in a respective manner. The design to be implementing by using Verilog-HDL language. The Simulation and Synthesis by using ISE Xilinx 13.4 tool.