Title :
Novel co-design of NAND flash memory and NAND flash controller circuits for sub-30nm low-power high-speed solid-state drives (SSD)
Author_Institution :
Dept. of Electron. Eng., Tokyo Univ., Tokyo
Abstract :
Three new circuit technologies, selective bit-line precharge scheme, advanced source-line program, and intelligent interleaving are proposed. By co-designing NAND flash memory and NAND controller circuits, both NAND and NAND controllers are best optimized. At sub-30 nm generation, the SSD speed improves by 150% without a cost penalty or circuit noise.
Keywords :
NAND circuits; flash memories; network synthesis; NAND flash controller circuits; NAND flash memory; advanced source-line program; intelligent interleaving; selective bit-line precharge; solid-state drives; Acceleration; Buffer storage; Capacitance; Circuit noise; Circuit synthesis; Costs; Interleaved codes; Power supplies; Random access memory; Solid state circuits;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585977
