Title :
Experimental evaluation of digital-circuit susceptibility to voltage variation in dynamic frequency scaling
Author :
Fukazawa, Mitsuya ; Kurimoto, Masanori ; Akiyama, Rei ; Takata, Hidehiro ; Nagata, Makoto
Author_Institution :
Kobe Univ., Kobe
Abstract :
Logical operations in CMOS digital integration are highly prone to fail as the amount of power-supply (PS) drop approaches to threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, in relation with instruction- level programming for logical failure analysis. Experimental measurements demonstrate that the increased susceptibility of processor operation with dynamic frequency scaling (DFS) can be mitigated through PS noise shaping.
Keywords :
CMOS digital integrated circuits; CMOS logic circuits; logic circuits; microprocessor chips; power supply circuits; CMOS digital integration; built-in noise monitors; digital-circuit susceptibility; dynamic frequency scaling; instruction- level programming; logical failure analysis; microprocessors; noise shaping; power-supply drop; size 90 nm; voltage variation; CMOS technology; Circuit testing; Clocks; Digital circuits; Dynamic voltage scaling; Failure analysis; Frequency; Microprocessors; Noise measurement; Noise shaping;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585986
