Time-to-digital converter with vernier delay mismatch compensation for high resolution on-die clock jitter measurement

A time-to-digital converter (TDC) utilizing a vernier delay line (VDL) technique has relatively large timing errors when the mismatch of the vernier delay is large. In order to overcome this problem, we propose a technique for compensating the vernier delay mismatch using multiple ring oscillation measurements of VDL. We verified it using an on-die jitter measurement circuit implemented in 90 nm CMOS technology and 0.880 ps timing resolution was obtained experimentally.