Title :
A 1.3-mW per-channel 103-dB SNR stereo audio DAC with class-D head-phones amplifier in 65nm CMOS
Author :
Lee, Yong-Hee ; Seok, Chun-Kyun ; Kim, Bong-Joo ; You, Seung-Bin ; Yeum, Wang-Seup ; Park, Ho-Jin ; Jun, Young-Hyun ; Kong, Bai-Sun ; Kim, Jae-Whui
Author_Institution :
Samsung Electron., Yongin
Abstract :
The stereo audio DAC with novel single-ended class-D amplifier achieving a 103-dB SNR is fully integrated in a 65 nm CMOS technology. Novel asymmetric pulse-width modulation (PWM) is applied to minimize switching noise and nonlinearity in the class-D amplifier. The adjustable delta-sigma modulator is also used to suppress supply-voltage modulation. All the functions needed for portable audio playback are implemented in a 0.53-mm2 area dissipating only 1.3-mW per channel from a 2.5-V supply.
Keywords :
CMOS integrated circuits; digital-analogue conversion; noise; pulse amplifiers; pulse width modulation; CMOS; class-D head-phones amplifier; pulse-width modulation; stereo audio DAC; switching noise; Delta modulation; Noise reduction; Noise shaping; Power amplifiers; Pulse amplifiers; Pulse width modulation; Pulse width modulation converters; Quantization; Signal to noise ratio; Space vector pulse width modulation; audio DAC; delta sigma and asymmetric PWM;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585996
