Channelizer structure in DRFM systems for real signals

In this paper, a channelized DRFM structure for DRFM(Digital Radio Frequency Memory) systems is presented. The novelty of this design is the modifications in the structure for supporting real signals without increasing the system delay. One of the most important parameters of a DRFMsystem is the system latency and the proposed architecture has less latency then the structures presented in the literature. The proposed architecture is implemented on a Virtex-6 SX475T and can run at 200 MHz clock speed.