Title :
A 14b 23MS/s 48mW resetting ΣΔ ADC with 87dB SFDR 11.7b ENOB & 0.5mm2 area
Author :
Lee, Chun C. ; Flynn, Michael P.
Author_Institution :
Dept. of EECS, Michigan Univ., Ann Arbor, MI
Abstract :
A 14 b 23 MS/s ADC that pipelines a 2nd order resetting SigmaDelta modulator with a 10 b cyclic ADC and requires no front-end S/H is presented. The architecture uses a resetting SigmaDelta modulator at the front-end for accuracy and a cyclic ADC at the back-end for residual error quantization. This calibration-free ADC achieves no missing codes, 87 dB SFDR and 11.7 b ENOB. Fabricated in 0.18 mum CMOS with a core area of 0.5 mm2, it consumes 48 mW from a 2 V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit manufacture; sample and hold circuits; sigma-delta modulation; CMOS; SigmaDelta ADC; SigmaDelta modulator; front-end S/H; power 48 mW; residual error quantization; size 0.18 mum; voltage 2 V; Bandwidth; Calibration; Capacitors; Circuits; Clocks; Energy consumption; Feeds; Frequency; Jitter; Pipeline processing;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4585999
