Memory yield and repair rate improvement scheme using built in self repair techniques

Author

Jyotika ; Singh, Bawa

Author_Institution

Centre for Dev. of Adv. Comput., Mohali, India

fYear

2014

fDate

28-29 Nov. 2014

Firstpage

350

Lastpage

354

Abstract

Memory is an important part of every computing system. In SOC, 90 to 92% of the total chip area is covered by embedded memories (ITRS 2009) and that means memory density is higher than the logic density. Therefore testing and diagnosis of memories are important issues in the SOCs. Yield of memory is affected by the faults present in memory which also affects the yield of SOC. Built in self-repair techniques are used to repair the embedded memories. Built in self-repair techniques are used for the better yield of the system by using various techniques like 1-D Redundancy and 2-D Redundancy. Test, Redundancy analysis, Repair delivery are the three basic steps for the memory repair. A built in redundancy algorithms (BIRA) are used to implement built in self-repair (BISR).

Keywords

built-in self test; integrated circuit reliability; integrated circuit yield; integrated memory circuits; redundancy; system-on-chip; BIRA; BISR technique; SOC; built-in redundancy algorithm; built-in self repair technique; embedded memory; logic density; memory density; memory diagnosis; memory fault; memory testing; memory yield; redundancy analysis; repair rate improvement scheme; system-on-chip; Algorithm design and analysis; Built-in self-test; Circuit faults; Maintenance engineering; Random access memory; Redundancy; System-on-chip; Built in redundancy analysis (BIRA); built in self-repair (BISR); built in self-test (BIST); embedded memories;

fLanguage

English

Publisher

ieee

Conference_Titel

Computational Intelligence on Power, Energy and Controls with their impact on Humanity (CIPECH), 2014 Innovative Applications of

Conference_Location

Ghaziabad

Type

conf

DOI

10.1109/CIPECH.2014.7019092

Filename

7019092