DSP architecture optimization in Matlab/Simulink environment

Author

Nanda, Rashmi ; Yang, Chia-Hsiang ; Markovic, Dejan

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, CA

fYear

2008

fDate

18-20 June 2008

Firstpage

192

Lastpage

193

Abstract

An automated architecture optimization for DSP algorithms within graphical Matlab/Simulink environment is proposed. The optimization uses Integer Linear Programming for scheduling and retiming of hardware blocks. The high-level block-diagram based Simulink model maps to FPGA or ASIC. Users can control the tuning range of architecture parameters and select solutions from energy-area-performance tradeoff space. The hierarchical method produces optimal architectures with energy efficiency of 5GOPS/mW in a 90 nm CMOS technology.

Keywords

application specific integrated circuits; digital signal processing chips; electronic engineering computing; field programmable gate arrays; integer programming; linear programming; ASIC; DSP architecture optimization; FPGA; graphical Matlab; high-level block-diagram based Simulink; integer linear programming; Application specific integrated circuits; Automatic control; CMOS technology; Digital signal processing; Field programmable gate arrays; Hardware; Integer linear programming; Mathematical model; Semiconductor device modeling; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2008 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1804-6

Electronic_ISBN

978-1-4244-1805-3

Type

conf

DOI

10.1109/VLSIC.2008.4586003

Filename

4586003