A 40-Gb/s transceiver in 0.13-μm CMOS technology

A fully integrated 40-Gb/s transceiver is implemented in a 0.13-mum CMOS technology. This paper describes the challenges in designing a 20-GHz input sampler, a 20-GHz quadrature LC-VCO, a 20-GHz bang-bang phase detector, and a 40-Gb/s equalizer. The transceiver occupies 1.7 times 2.9 mm² and dissipates 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2¹⁵-1 PRBS data is 1.85 ps_rms over a wire-bonded plastic ball grid array (PBGA) package, an 8-mm RO-4350B PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable, while the recovered clock jitter is 1.77 ps_rms. The measured BER is < 10^-14.