• DocumentCode
    2376002
  • Title

    A teraBit/s-throughput, SerDes-based interface for a third-generation 16 core 32 thread chip-multithreading SPARC processor

  • Author

    Nasrullah, Jawad ; Amin, Arif ; Ahmad, Waseem ; Qin, Zuxu ; Mushtaq, Zahid ; Javed, Osman ; Yoon, Joon ; Chua, Leandro ; Huang, Dawei ; Huang, Baoqing ; Vichare, Makarand ; Ho, Kenneth ; Rashid, Mamun

  • Author_Institution
    Sun Microsyst., Santa Clara, CA
  • fYear
    2008
  • fDate
    18-20 June 2008
  • Firstpage
    200
  • Lastpage
    201
  • Abstract
    Third-generation 16 core 32 thread chip-multithreading SPARC processor interface has 1.1 Tbps I/O throughput with 112 Tx/176 Rx SerDes channels in 46 mm2. Individual links run at BER of 1E-12 on FR4 PCBs at 4.08-0.5 Gbps full-half rate, and 18 mW/ch/Gbps at 2.67 Gbps. Each link has linear equalization, 15 deemphasis and 8 output-swing control settings, and latency of 8UI in Rx and 14-16UI in Tx.
  • Keywords
    error statistics; input-output programs; microprocessor chips; printed circuits; BER; FR4 PCB; I/O throughput; SPARC processor; SerDes channels; SerDes-based interface; chip-multithreading processor; linear equalization; third-generation processor; Area measurement; Bit error rate; Clocks; Delay; Equalizers; Phase locked loops; Power measurement; Throughput; Velocity measurement; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2008 IEEE Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-1804-6
  • Electronic_ISBN
    978-1-4244-1805-3
  • Type

    conf

  • DOI
    10.1109/VLSIC.2008.4586006
  • Filename
    4586006
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2376002