A 21-channel 8Gb/s transceiver macro with 3.6ns latency in 90nm CMOS for 80cm backplane communication

Author

Hayashi, Atsuhiro ; Kuwata, Makoto ; Suzuki, Kazuhisa ; Muto, Takashi ; Tsuge, Masatoshi ; Nagashima, Kazuhito ; Hamano, Daisuke ; Usugi, Tatsunori ; Nakajima, Kazunori ; Ogihara, Masao ; Mikami, Norihisa ; Watanabe, Keiki

Author_Institution

Micro Device Div., Hitachi, Ltd., Tokyo

fYear

2008

fDate

18-20 June 2008

Firstpage

202

Lastpage

203

Abstract

A 21-channel 8 Gb/s transceiver is implemented in a 90 nm CMOS technology. 168 Gb/s uncoded data transmission with 3.6 ns latency is achieved with 4-tap FFE, receiver equalization, jitter tolerant CDR and low jitter PLL. Measured bathtub plots for 80 cm FR-4 backplane indicate BER<10^-15 with 0.11 UI phase margin at the nominal power consumption of 160 mW/ch.

Keywords

CMOS integrated circuits; integrated circuit design; transceivers; CMOS; FFE; backplane communication; bit rate 168 Gbit/s; bit rate 8 Gbit/s; jitter tolerant CDR; low jitter PLL; power consumption; receiver equalization; size 80 cm; time 3.6 ns; transceiver macro; uncoded data transmission; wavelength 90 nm; Backplanes; CMOS technology; Data communication; Delay; Energy consumption; Jitter; Phase locked loops; Phase measurement; Power measurement; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2008 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1804-6

Electronic_ISBN

978-1-4244-1805-3

Type

conf

DOI

10.1109/VLSIC.2008.4586007

Filename

4586007