Title :
A high performance 2.4 Mb L1 and L2 cache compatible 45nm SRAM with yield improvement capabilities
Author :
Joshi, R. ; Houle, R. ; Rodko, D. ; Patel, P. ; Huott, W. ; Franch, R. ; Chan, Y. ; Plass, D. ; Wilson, S. ; Wu, S. ; Kanj, R.
Author_Institution :
IBM Res., Yorktown Heights, NY
Abstract :
A hardware based, fully functional, stable 2.4 Mb L1 and L2 Cache compatible 6T embedded SRAM is demonstrated. Measured results show an operating range of -40degC to 120degC, speed of 6.5 GHz and 3.8 GHz for L1-Cache cells and L2-Cache cells, respectively, at 1 V and 25degC, with high yield. The key features include multi-setting programmable clock block, separate read/write margin circuitry, low noise dynamic decoders, bit select circuitry supported by newly developed fast Monte Carlo technique useful for improved cell stability, writeability, and enhanced yield. A novel Burst Mode feature allows defect analysis at high frequency while using slow tester speeds.
Keywords :
Monte Carlo methods; SRAM chips; cache storage; embedded systems; integrated circuit yield; logic design; 6T embedded SRAM; L1 cache; L2 cache; Monte Carlo technique; bit select circuitry; burst mode feature; cell stability; defect analysis; frequency 3.8 GHz; frequency 6.5 GHz; low noise dynamic decoders; multisetting programmable clock block; read/write margin circuitry; size 45 nm; storage capacity 2.4 Mbit; temperature -40 C to 120 C; voltage 1 V; yield improvement capabilities; Circuit noise; Circuit stability; Circuit testing; Clocks; Decoding; Frequency; Hardware; Monte Carlo methods; Random access memory; Velocity measurement;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4586009