Title :
A process-scalable low-power charge-domain 13-bit pipeline ADC
Author :
Anthony, Michael ; Kohler, Edward ; Kurtze, Jeffrey ; Kushner, Lawrence ; Sollner, Gerhard
Author_Institution :
Kenet, Inc., Woburn, MA
Abstract :
A 13-bit ADC is implemented using a novel charge-domain architecture. Enhanced bucket-brigade circuitry and a tapered charge pipeline provide precision charge-domain operation in a standard CMOS process, while eliminating the need for signal-path op-amps. The prototype ADC, implemented in 0.18 mum CMOS, provides 10.65 ENOB at 250 MS/s while consuming only 140 mW, yielding an exceptionally low FoM of 0.28 pJ/conversion-step. Simulations indicate that the architecture and circuitry are well suited to scaling below 90 nm.
Keywords :
CMOS integrated circuits; analogue-digital conversion; operational amplifiers; CMOS process; bucket-brigade circuitry; charge-domain architecture; pipeline ADC; power 140 mW; signal-path op-amps; size 0.18 mum; tapered charge pipeline; word length 13 bit; CMOS process; Charge transfer; Circuit simulation; Energy consumption; Equations; FETs; Operational amplifiers; Pipeline processing; Switched capacitor circuits; Voltage;
Conference_Titel :
VLSI Circuits, 2008 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1804-6
Electronic_ISBN :
978-1-4244-1805-3
DOI :
10.1109/VLSIC.2008.4586015
