Statistical Power Estimation for IP-Based Design

In this work, we present a power macromodeling technique for register transfer level model of digital circuits. This technique is applied to the statistical knowledge of the primary inputs/outputs of the intellectual property (IP) components. During power estimation procedure, the sequence of an input stream is generated using input metrics and the macromodel function is used to construct a set of functions that maps the input metrics of a macro-block to its output metrics. Monte Carlo zero delay simulation is performed and power dissipation is predicted by a power macromodel function. In experiments with the IP blocks, the results are effective and highly correlated, with an average error of 1.84%. Our model provides accurate power estimation