DocumentCode
2376679
Title
Efficient embedded memory testing with APG
Author
Sivaram, A.T. ; Fan, Daniel ; Yiin, A.
Author_Institution
NPTest, San Jose, CA, USA
fYear
2002
fDate
2002
Firstpage
47
Lastpage
54
Abstract
This paper describes the unique hardware features designed in a traditional hardware Algorithmic Pattern Generator (APG) to make full functional Direct Access Testing (DAT) of embedded memories with different data widths easier in a high volume production environment. The APG support software enables the encapsulation of pattern design for various sizes of embedded memories or arrays to significantly reduce the pattern complexity and generation effort.
Keywords
automatic testing; built-in self test; integrated circuit testing; integrated memory circuits; logic testing; production testing; system-on-chip; data width mask implementation; direct access testing; embedded memory testing; hardware algorithmic pattern generator; high volume production environment; latency delay implementation; memory BIST; Algorithm design and analysis; Bandwidth; Circuit testing; Electronic equipment testing; Embedded software; Hardware; Manufacturing; Robustness; System testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2002. Proceedings. International
ISSN
1089-3539
Print_ISBN
0-7803-7542-4
Type
conf
DOI
10.1109/TEST.2002.1041744
Filename
1041744
Link To Document