IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips

To enable the efficient use of debug functionality on a core-based system chip, existing core-level debug interfaces need to be re-used in one, well-defined debug architectures at chip-level. This paper describes a chip-level architecture for controlling multiple IEEE 1149.1 compliant debug interfaces on a single system chip. The presented architecture is not only fully compliant with IEEE 1149.1 with regard to the chip-level debug and boundary scan hardware, but also as to whether or not the bypass multiplexer is activated. Chip-level TAP support is also presented to allow multiple debugger tools to control debug operations in multiple heterogeneous cores via this architecture. As an experiment, the proposed architecture is mapped on an FPGA to verify concurrent debug of multiple cores.