Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm

Author

Huang, Yu ; Reddy, Sudhakar M. ; Cheng, Wu-Tung ; Reuter, Paul ; Mukherjee, Nilanjan ; Tsai, Chien-Chung ; Samman, Omer ; Zaidan, Yahya

Author_Institution

Mentor Graphics Corp., Wilsonville, OR, USA

fYear

2002

fDate

2002

Firstpage

74

Lastpage

82

Abstract

This paper presents a method to consider a given SOC with pin and peak power constraints, and simultaneously (1) determine an optimal wrapper width for each core, (2) allocate SOC pins to cores and (3) schedule core tests to minimize the test completion time. For the first time the stated problem is formulated as a restricted 3 dimensional bin-packing problem and a heuristic to determine an optimal solution is proposed.

Keywords

bin packing; circuit CAD; circuit optimisation; integrated circuit design; integrated circuit testing; logic CAD; logic testing; performance evaluation; scheduling; system-on-chip; 3D bin packing algorithms; SOC pin/peak power constraints; SOC test scheduling; TAM; benchmark testing; optimal core wrapper width selection; optimal solution heuristic algorithm; pins/core allocation; restricted 3D bin-packing problems; test access mechanisms; test time minimization; Circuit testing; Cities and towns; Computer graphics; Intellectual property; Pins; Power engineering and energy; Power engineering computing; Processor scheduling; Scheduling algorithm; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2002. Proceedings. International

ISSN

1089-3539

Print_ISBN

0-7803-7542-4

Type

conf

DOI

10.1109/TEST.2002.1041747

Filename

1041747