On testing of interconnect open defects in combinational logic circuits with stems of large fanout

We consider the problem of testing of interconnect open defects in combinational circuits with large fanout nodes. We propose a gate level fault model for interconnect opens. The number of interconnect open faults using the proposed model can be very large, being exponential in the fanout size. We describe methods to effectively consider the very large numbers of open faults. These methods include techniques for implicit consideration of open faults, and the use of information about fanout branches driving each primary output to reduce the list of faults. We present experimental results to demonstrate that fault simulation and test generation for the modeled open faults can be carried out efficiently using these techniques.