Test point insertion that facilitates ATPG in reducing test time and data volume

Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means of test point insertion (TPI). The state-of-the-art TPI methods only focus on solving one or two possible testability problems, and sometimes even fail to result in test set size reduction because they focus on the wrong testability problem. In this paper, we propose two TPI pre-process methods that analyze the circuit and select the TPI method that will focus on the testability problems that really exist. Experimental results indicate that with these pre-processes, better test set size reductions can be achieved. Gate-delay fault ATPG test sets tend to be even larger than stuck-at fault ATPG test sets. In this paper we have evaluated the impact of TPI on gate-delay fault test sets. Experimental results indicate that TPI also results in a significant test set size reduction for gate-delay fault ATPG.