• DocumentCode
    2376954
  • Title

    Integration of SRAM redundancy into production test

  • Author

    Jayabalan, Jayasanker ; Povazanec, Juraj

  • Author_Institution
    Dev. Center, Transceivers Infineon Technol. Asia Pacific Pte Ltd., Singapore, Singapore
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    187
  • Lastpage
    193
  • Abstract
    In this paper, we present the implementation of a multiple-SRAM redundancy concept, which increases the yield of a 100 mm2, 0.18 micron technology device with a total memory size of 3 Mbits, by a factor of 20%. A number of test and design considerations are detailed.
  • Keywords
    SRAM chips; built-in self test; integrated circuit design; integrated circuit testing; integrated circuit yield; production testing; redundancy; system-on-chip; 0.18 micron; 3 Mbit; BIST; MBIST; SOC applications; SRAM redundancy; memory built-in self-test; memory size; multiple-SRAM redundancy concept; redundancy production test integration; system-on-chip devices; yield increase; Asia; Circuit faults; Circuit testing; Fuses; Logic; Production; Random access memory; Redundancy; Registers; Transceivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2002. Proceedings. International
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-7542-4
  • Type

    conf

  • DOI
    10.1109/TEST.2002.1041760
  • Filename
    1041760
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2376954