Title :
Design rewiring using ATPG
Author :
Veneris, Andreas ; Abadir, Magdy S. ; Amiri, Mandana
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
Technology dependent logic optimization is usually carried through a sequence of design rewiring operations. In Veneris et al (Proc. Asian-South-Pacific Design Automation Conf., pp. 479-484, 2001), a new design rewiring method is proposed that combines error diagnosis and correction techniques with ATPG. In this work, we examine its complexity and we arrive to a new set of results with interesting theoretical and practical applications. We also present experiments that confirm the competitiveness of the approach and motivate future work in the field.
Keywords :
automatic test pattern generation; circuit layout CAD; circuit optimisation; computational complexity; error correction; error detection; integrated circuit design; logic CAD; ATPG; complexity; design rewiring method; design rewiring operation sequence; error correction techniques; error diagnosis; technology dependent logic optimization; Automatic test pattern generation; Circuit faults; Circuit testing; Constraint optimization; Design optimization; Error correction; Logic design; Logic testing; Redundancy; Wire;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041764
