VLSI implementation of reduced resource allocation for modified carry look-ahead adder

With the increase in the VLSI technology level the system level designs are becoming too complex by effect of brutal design of low level complex design. The reduction in resources allocated to implement the system contributes to the significant decrease in the design complexity. In this paper, a new methodology is proposed for carry look-ahead adder to quarry the mitigation of resources required to implement the proposed adder. The implementation of the adder is carried on both Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) platforms. The proposed methodology presents the delay efficient adder simultaneously reducing the power consumption by decreasing the resources as its deliverables.